Zoom V3 1612 Manual de usuario Pagina 110
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BIT1612 10-Bit Digital Video Decoder with OSD and T-CON
100
R_LINE_CUT_M1......................................................35
R_LINE_THD1...........................................................48
R_LINE_THD2...........................................................48
R_LINEBUF_CKEN ...................................................15
R_LN1CLK_POL .......................................................16
R_LN2CLK_POL .......................................................16
R_LN3CLK_POL .......................................................16
R_LN4CLK_POL .......................................................15
R_LN5CLK_POL .......................................................15
R_LOAD_EN ............................................................. 11
R_LOAD_TYPE ......................................................... 11
R_LOWER_BOUND ..................................................47
R_LTPS_MODE ........................................................21
R_MASTER_DLY_M0 ...............................................35
R_MASTER_DLY_M1 ...............................................35
R_MCLK_EN .............................................................14
R_MCLK_POL ...........................................................14
R_MCLK_SEL ...........................................................14
R_MCU_DEBUG ................................................. 80, 86
R_MODE_TYPE ........................................................74
R_MODECHG ...........................................................74
R_MV_DET_CHROMA..............................................57
R_MV_DET_SYNC....................................................57
R_MV_TYPE_CHROMA ...........................................57
R_N44360_AUTOSW................................................48
R_NOCOR_AUTOSW ...............................................48
R_NOSIG_SEL..........................................................24
R_OCLK_TRI.............................................................12
R_OEH_END.............................................................20
R_OEH_GATE...........................................................20
R_OEH_START.........................................................20
R_OS_XP ..................................................................16
R_OS_XS ..................................................................16
R_OS_XT_M0 ...........................................................16
R_OS_XT_M1 ...........................................................16
R_OS_XW .................................................................16
R_OS_YP ..................................................................16
R_OS_YS ..................................................................16
R_OS_YT ............................................................16, 19
R_OS_YW .................................................................16
R_OSD_LAYER .........................................................67
R_OSDCLK_EN.........................................................69
R_OSDCLK_POL ......................................................69
R_OUT_DACMAP_LB ...............................................39
R_OUT_DACMAP_SPACE .......................................39
R_OUT_SEL ..............................................................48
R_PAL_SENSITIVE...................................................47
R_PCLK_BASE .........................................................30
R_PCLK_EN ..............................................................14
R_PCLK_POL............................................................14
R_PCLK_SEL ............................................................14
R_PG_EN ............................................................79, 85
R_PG_POL................................................................79
R_PLL_DM_M0 .........................................................73
R_PLL_DM_M1 .........................................................73
R_PLL_DN_M0..........................................................73
R_PLL_DN_M1..........................................................73
R_PLL_DP_M0..........................................................73
R_PLL_DP_M1..........................................................73
R_PLL_EAPLL...........................................................53
R_PLL_HALFCK........................................................73
R_PLL_ICP0..............................................................53
R_PLL_ICP1..............................................................53
R_PLL_PD.................................................................72
R_PLL_POR ..............................................................53
R_PLL_RESETN .......................................................72
R_PLL_SEL ...............................................................73
R_PLLDTO_ROL .......................................................53
R_POF.......................................................................80
R_POL_BIN ...............................................................25
R_POL_BOUT ...........................................................17
R_POL_CKV..............................................................20
R_POL_EXTBNK.......................................................68
R_POL_FRP ..............................................................20
R_POL_GIN...............................................................25
R_POL_GOUT...........................................................17
- BIT1612 1
- Content 2
- 1 General Description 11
- 2 Features 11
- 3 Order Information 13
- 4 Block Diagram 13
- 5 Pin Definition 14
- 6 Functional Description 18
- 6.4 Pad Type Setup 22
- 6.6 System Enable and Reset 23
- 6.7 Clock Domain Systems 24
- Panel Active Window 26
- Blank Range 26
- HSYNC Output 26
- VSYNC Output 26
- 6.9 Output Data Path 27
- 6.10 Special Output Setup 28
- Input VSYNC 29
- Output VSYNC 29
- 6.12 TCON Function 30
- 6.15 Background 2 33
- 6.17 Auto Blank Screen 34
- Input Image Window 35
- HSYNC Input 35
- VSYNC Input 35
- (Internal VD) 36
- R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 37
- G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 37
- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 37
- 6.20.7 RGB565 38
- 6.21 Input Mode Selection 39
- Background 41
- 6.24 Scaling Engine 42
- 6.25 Timing Adjustment 45
- Pre-Image Enhancement 46
- Post-Image Enhancement 46
- 6.26.3 Sharpness Process 47
- 6.26.7 LUT Gamma Correction 48
- 6.26.8 Dither 48
- Factor 0x80 49
- 6.27 PWM Function 50
- R_PWM_REF 51
- Base on panel clock 51
- R_PWM_FREQ 51
- R_PWM_DUTY 51
- Base on reference clock 51
- 6.28.5 VBI Data Slicer 55
- 6.28.6 Source Detection 55
- 6.28.7 Luminance Process 56
- 6.28.8 Chroma Process 57
- 6.28.9 Comb Filter Process 58
- 6.28.10 AGC and ACC Process 60
- 6.28.11 AFE and PLL Control 63
- 6.30 Serial RGB Output 68
- 6.31 BIT1690 Interface 68
- 6.32 OSD Function 69
- 6.32.2 OSD Memory Mapping 70
- R_Wx_INDEXS 71
- R_Wx_INDEXE 71
- R_BANK_SEL = 000 72
- If Display RAM 72
- {0x503[4],0x403[6:0]} = 72
- {0x501[4],0x401[6:0]} 73
- R_Wx_INDEX_S 76
- R_OSD_LAYER[2:0] = 001 77
- 6.32.7 OSD Clock Control 79
- 6.33 Timer 80
- 6.34 IR Decoder Function 81
- 6.35 GPI and KEY Function 82
- 6.36 PLL and OSC Pads 82
- 6.37 Auto Detection 83
- 01: From VSYNC1 Pin 85
- 10: From HSYNC2 Pin 85
- 11: From VSYNC2 Pin 85
- 7 User Interface 86
- 7.2.1 Architecture 89
- 7.2.2 Instruction Set 91
- 7.2.3 Start and Interrupt 94
- 7.2.6 Watch Dog Timer 95
- 7.2.8 TWSI Write/Read 96
- 7.2.9 SPI Interface 96
- 7.2.10 Debug Mode 96
- 7.3 Slave Mode 97
- 7.3.2 TWSI Protocol 98
- From Pin 104 Setting 100
- From Pin 105 Setting 100
- 8 Timing Diagram 101
- 9 Electrical Characteristic 103
- 10 Soldering Information 104
- 11 Package Information 105
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