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BIT1612 10-Bit Digital Video Decoder with OSD and T-CON

6.28.11 AFE and PLL Control

BIT1612 內建 AFE (Analog Front End) 設定參數，相關設定請參考下表。

Table 6-51 ADC Control Register

Mnemonic Address R/W Bits Description Default

R_AFE_CS 0x0EC[1:0] RW 2 AFE Clamp Current 00

R_AFE_CTRPH 0x0EC[3:2] RW 2 AFE Phase Non-Overlap Time 00

R_AFE_CTRIB 0x0EC[6:4] RW 3 AFE Bias Current Control 110

R_AFE_SH2VCM 0x0EC[7] RW 1 AFE Internal Shortcut On both PGA 0

R_AFE_ENIB 0x0ED[0] RW 1 AFE Bias Current Enable 1

R_AFE_ENREF 0x0ED[1] RW 1 AFE Reference Generator Enable 1

R_AFE_ENVBG 0x0ED[2] RW 1 AFE Bandgap Generator Enable 1

R_AFE_ENVCM 0x0ED[3] RW 1

AFE Common Mode Voltage Generator

Enable

Power Down Input for ADC 1

0: Power Down

R_AFE_ENAY 0x0ED[4] RW 1

1: Normal Operation

Power Down Input for ADC 2

0: Power Down

R_AFE_ENAC 0x0ED[5] RW 1

1: Normal Operation

R_AFE_BYP 0x0ED[6] RW 1 Bypass PGA for ADC Test 0

R_AFE_DEC 0x0ED[7] RW 1

Control Output Data Decimator by 8 or None

(Dec = 0: Normal Operation)

PLL Power On Reset

0: Disable

R_PLL_POR 0x0EE[0] RW 1

1: Reset

PLL Enable

0: Disable

R_PLL_EAPLL 0x0EE[1] RW 1

1: Enable

R_PLL_ICP0 0x0EE[2] RW 1 PLL Factor 0 0

R_PLL_ICP1 0x0EE[3] RW 1 PLL Factor 1 0

PLL DTO Rotate

0: Disable

R_PLLDTO_ROL 0x0EE[4] RW 1

1: Enable

1 2 ... 58 59 60 61 62 63 64 65 66 67 68 ... 114 115

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