Zoom V3 1612 Manual de usuario descargar pdf (Pagina 25)

BIT1612 10-Bit Digital Video Decoder with OSD and T-CON

1: Enable

DAC Clock Domain Enable

0: Disable

R_DACCLK_EN 0x00B[2] RW 1

1: Enable

DAC Clock Domain Polarity

0: Normal

R_DACCLK_POL 0x00B[3] RW 1

1: Invert

LCLK x 4 Enable

0: Disable

R_LCLK_4X 0x00B[7] RW 1

1: Enable

LINEBUF Clock Enable

0: Disable

R_LINEBUF_CKEN 0x00D[1] RW 1

1: Enable

Registers set Clock Enable

0: Disable

R_REGS_CKEN 0x00D[2] RW 1

1: Enable

VD Clock Domain Clock Source Selection

0: From 27MHz

R_VDCLK_SEL 0x00D[3] RW 1

1: From 13.5MHz

AFE Buffer Clock Domain Clock Source Selection

0: From DVPCLK.

R_AFEBUF_SEL 0x00F[6] RW 1

1: From AFECLK

AFE Buffer Clock Domain Polarity

0: Normal

R_AFEBUF_POL 0x00F[7] RW 1

1: Invert

AFE Clock Domain Clock Source Selection

0: From 27MHz

R_AFECLK_SEL 0x00F[4] RW 1

1: From 13.5MHz

AFE Clock Domain Polarity

0: Normal

R_AFECLK_POL 0x00F[5] RW 1

1: Invert

AFE Clock Domain Enable

0: Disable

R_AFECLK_EN 0x00F[3] RW 1

1: Enable

DVP Clock Domain Clock Source Selection

0: From PLL

R_DVPCLK_SEL 0x00F[1] RW 1

1: From OSC

DVP Clock Domain Polarity

0: Normal

R_DVPCLK_POL 0x00F[2] RW 1

1: Invert

DVP Clock Domain Enable

0: Disable

R_DVPCLK_EN 0x00F[0] RW 1

1: Enable

CLK27 Domain Polarity

0: Normal

R_CLK27_POL 0x0EF[0] RW 1

1: Invert

CLK27 Domain Enable

0: Disable

R_CLK27_EN 0x0EF[1] RW 1

1: Enable

Line Buffer Clock 5 Polarity

0: Normal

R_LN5CLK_POL 0x0F7[4] RW 1

1: Invert

Line Buffer Clock 4 Polarity

0: Normal

R_LN4CLK_POL 0x0F7[3] RW 1

1: Invert

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 114 115

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Zoom V3 1612 Manual de usuario Pagina 25

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