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BIT1612 10-Bit Digital Video Decoder with OSD and T-CON

6.28.5 VBI Data Slicer

BIT1612 提供 Data Slicer 功能可依據針對所設定的 Lines 及 Even/Odd，分離出 16 Bits 的 Data，並

且經由 Interrupt 及 Register 提供 MCU 做後續處理，相關的 Registers 請參考下表。

Table 6-45 VBI Data Slicer Process Register

Mnemonic Address R/W Bits Description Default

R_DATA_SLICER_THD 0x0C0[7:0] RW 8 Data Slicer High/Low Threshold 0x26

R_DATA_SLICER_START 0x0C1[7:0] RW 8 Data Slicer Start Point 0x99

R_DATA_SLICER_LINE_E 0x0C2[5:0] RW 6 Data Slicer Line Selection for Even Field 0x11

Data Slicer Enable for Even Field

0: Disable

R_DATA_SLICER_EN_E 0x0C2[7] RW 1

0: Enable

R_DATA_SLICER_LINE_O 0x0C3[5:0] RW 6 Data Slicer Line Selection for Odd Field 0x10

Data Slicer Enable for Odd Field

0: Disable

R_DATA_SLICER_EN_O 0x0C3[7] RW 1

0: Enable

Data Slicer Output (0x17A, 0x17B) Selection

0: Even Field

R_CC_DATA_SEL 0x17C[7] RW 1

1: Odd Field

R_CC_DATA1 0x17A[7:0] R 8 Data Slicer First Byte -

R_CC_DATA2 0x17B[7:0] R 8 Data Slicer Second Byte -

6.28.6 Source Detection

BIT1612 提供Source Detection 的功能可以自動偵測AIN11 (SRC11)、AIN12 (SRC12)和AIN2 (SRC2)

何者輸入有信號的變化，偵測的結果將經由 Interrupt 提供系統使用，相關的 Registers 設定請參考下表。

Table 6-46 Source Detection Process Register

Mnemonic Address R/W Bits Description Default

R_CH2_THD 0x0C4[1:0] RW 2 Signal detection threshold for AIN2 00

R_CH12_THD 0x0C4[3:2] RW 2 Signal detection threshold for AIN12 00

R_CH11_THD 0x0C4[5:4] RW 2 Signal detection threshold for AIN11 00

Source Detection Mode

0: Disable (Normal Mode)

R_SRCDET_MODE 0x0C4[7] RW 1

1: Source Detection Mode

R_SRC2 0x178[4] R 1 Source detection result for AIN2 -

R_SRC12 0x178[5] R 1 Source detection result for AIN12 -

Source detection result for AIN11

0: No signal toggle

R_SRC11 0x178[6] R 1

1: Signal toggle

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