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BIT1612 10-Bit Digital Video Decoder with OSD and T-CON
14
6.7 Clock Domain Systems
BIT1612 內部存在五個 Clock Domain：
1. PCLK Domain: Source Clock
2. LCLK Domain: Output Clock
3. XCLK Domain: System Clock
4. MCLK Domain: Image Clock
5. TCLK Domain: Panel Clock
相關Registers設定請參考
Table 6-10。
注意事項：XCLK Domain 頻率必須比 LCLK Domain 低。
Table 6-10 Clock Domain System Register
Mnemonic Address R/W Bits Description Default
R_XCLK_SEL 0x00B[6:4] RW 3
XCLK Domain Clock Source Selection
XCLK = OSCCLK / (2^R_XCLK_SEL)
000
TCLK Domain Clock Source Selection
000: PLLCLK
001: OSCCLK
010: ICLK1
011: ICLK2
R_TCLK_SEL 0x00C[2:0] RW 3
1xx: VDCLK
001
TCLK Domain Polarity
0: Normal.
R_TCLK_POL 0x00C[3] RW 1
1: Invert.
0
TCLK Domain Enable
0: Disable.
R_TCLK_EN 0x00C[4] RW 1
1: Enable.
1
LCLK Domain Clock Source Selection
00: Normal Clock (Freq. equals to LCLK)
01: Phase 1 Clock (Freq. equals to LCLK/3)
10: Phase 2 Clock (Freq. equals to LCLK/3)
R_LCLK_SEL 0x00D[5:4] RW 2
11: Phase 3 Clock (Freq. equals to LCLK/3)
10
LCLK Domain Polarity
0: Normal
R_LCLK_POL 0x00D[6] RW 1
1: Invert
0
LCLK Domain Enable
0: Disable
R_LCLK_EN 0x00D[7] RW 1
1: Enable
1
MCLK Domain Clock Source Selection
R_MCLK_SEL 0x00E[1:0] RW 2
MCLK = PCLK / (R_MCLK_MODE+1)
01
MCLK Domain Polarity
0: Normal
R_MCLK_POL 0x00E[2] RW 1
1: Invert
1
MCLK Domain Enable
0: Disable
R_MCLK_EN 0x00E[3] RW 1
1: Enable
1
PCLK Domain Clock Source Selection
00: ICLK1
01: ICLK2
R_PCLK_SEL 0x00E[5:4] RW 2
1x: VDCLK
00
PCLK Domain Polarity
0: Normal
R_PCLK_POL 0x00E[6] RW 1
1: Invert
1
PCLK Domain Enable R_PCLK_EN 0x00E[7] RW 1
0: Disable
1
- BIT1612 1
- Content 2
- 1 General Description 11
- 2 Features 11
- 3 Order Information 13
- 4 Block Diagram 13
- 5 Pin Definition 14
- 6 Functional Description 18
- 6.4 Pad Type Setup 22
- 6.6 System Enable and Reset 23
- 6.7 Clock Domain Systems 24
- Panel Active Window 26
- Blank Range 26
- HSYNC Output 26
- VSYNC Output 26
- 6.9 Output Data Path 27
- 6.10 Special Output Setup 28
- Input VSYNC 29
- Output VSYNC 29
- 6.12 TCON Function 30
- 6.15 Background 2 33
- 6.17 Auto Blank Screen 34
- Input Image Window 35
- HSYNC Input 35
- VSYNC Input 35
- (Internal VD) 36
- R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 37
- G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 37
- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 37
- 6.20.7 RGB565 38
- 6.21 Input Mode Selection 39
- Background 41
- 6.24 Scaling Engine 42
- 6.25 Timing Adjustment 45
- Pre-Image Enhancement 46
- Post-Image Enhancement 46
- 6.26.3 Sharpness Process 47
- 6.26.7 LUT Gamma Correction 48
- 6.26.8 Dither 48
- Factor 0x80 49
- 6.27 PWM Function 50
- R_PWM_REF 51
- Base on panel clock 51
- R_PWM_FREQ 51
- R_PWM_DUTY 51
- Base on reference clock 51
- 6.28.5 VBI Data Slicer 55
- 6.28.6 Source Detection 55
- 6.28.7 Luminance Process 56
- 6.28.8 Chroma Process 57
- 6.28.9 Comb Filter Process 58
- 6.28.10 AGC and ACC Process 60
- 6.28.11 AFE and PLL Control 63
- 6.30 Serial RGB Output 68
- 6.31 BIT1690 Interface 68
- 6.32 OSD Function 69
- 6.32.2 OSD Memory Mapping 70
- R_Wx_INDEXS 71
- R_Wx_INDEXE 71
- R_BANK_SEL = 000 72
- If Display RAM 72
- {0x503[4],0x403[6:0]} = 72
- {0x501[4],0x401[6:0]} 73
- R_Wx_INDEX_S 76
- R_OSD_LAYER[2:0] = 001 77
- 6.32.7 OSD Clock Control 79
- 6.33 Timer 80
- 6.34 IR Decoder Function 81
- 6.35 GPI and KEY Function 82
- 6.36 PLL and OSC Pads 82
- 6.37 Auto Detection 83
- 01: From VSYNC1 Pin 85
- 10: From HSYNC2 Pin 85
- 11: From VSYNC2 Pin 85
- 7 User Interface 86
- 7.2.1 Architecture 89
- 7.2.2 Instruction Set 91
- 7.2.3 Start and Interrupt 94
- 7.2.6 Watch Dog Timer 95
- 7.2.8 TWSI Write/Read 96
- 7.2.9 SPI Interface 96
- 7.2.10 Debug Mode 96
- 7.3 Slave Mode 97
- 7.3.2 TWSI Protocol 98
- From Pin 104 Setting 100
- From Pin 105 Setting 100
- 8 Timing Diagram 101
- 9 Electrical Characteristic 103
- 10 Soldering Information 104
- 11 Package Information 105
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