Zoom V3 1612 Manual de usuario Pagina 19
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BIT1612 10-Bit Digital Video Decoder with OSD and T-CON
9
Table 6-3 Interrupt Controller Register
Mnemonic Address R/W Bits Description Default
Interrupt Flag
0: Nothing
R_INT_FLAG 0x002[7:0] R 8
1: Interrupt Event Occurs
-
Interrupt MASK (see Figure 6-1)
0: Interrupt Mask Off (Enable Interrupt)
R_INT_MASK 0x003[7:0] RW 8
1: Interrupt Mask On (Disable Interrupt)
0x00
Interrupt ACK (see Figure 6-1)
0: Clear Interrupt Flag and Disable Interrupt
R_INT_ACK 0x004[7:0] RW 8
1: Enable Interrupt
0x00
Interrupt TYPE
0: Level Type
R_INT_TYPE 0x005[0] RW 1
1: Edge Type
0
Interrupt Polarity
0: High Level Active (Level Type)
0: Rising Edge Active (Edge Type)
1: Low Level Active (Level Type)
R_POL_INT 0x005[1] RW 1
1: Falling Edge Active (Edge Type)
0
Interrupt Vector[0] and Vector[1]
Source Selection
0: From VP
R_INTSIGIN_SEL 0x0FB[5] RW 1
1: From VD
0
Interrupt Vector[2] Source Selection
0: From VP
R_INTMODECHG_SEL 0x0FB[6] RW 1
1: From VD
0
Interrupt Vector[3] Source Selection
00: VSYNC from Input VSYNC Source
01: VSYNC from Output VSYNC Source
10: VSYNC from VD VSYNC Source
R_INT_VSSE 0x005[3:2] RW 2
11: VSYNC Source Active when TWSI
Detection Occurs.
00
Interrupt Vector[3] Polarity Selection
0: Normal
R_INTVS_POL 0x005[4] RW 1
1: Invert
0
Interrupt Vector[5] VP Error Source Enable
0: Disable
R_VP_ERR2_EN 0x006[3] RW 1
1: Enable
0
Interrupt Vector[4] and Vector[5]
Source Selection
0: From Timer Overflow
R_INT_ERRSEL 0x006[4] RW 1
1: From Line Buffer Error
0
Line Buffer Error Detection Selection
0: ODD Field
R_ERROR_TYPE 0x006[5] RW 1
1: EVEN Field
0
IHS Pulse Width Selection
0: Type 0
R_IHSPS_SEL 0x04D[7] RW 1
1: Type 1
0
Table 6-4 Video Decoder Lock Source for Interrupt Selection
Mnemonic Address R/W Bits Description Default
HLCK Detection Enable
0: Disable
R_INTHLCK_EN 0x0FB[0] RW 1
1: Enable
0
- BIT1612 1
- Content 2
- 1 General Description 11
- 2 Features 11
- 3 Order Information 13
- 4 Block Diagram 13
- 5 Pin Definition 14
- 6 Functional Description 18
- 6.4 Pad Type Setup 22
- 6.6 System Enable and Reset 23
- 6.7 Clock Domain Systems 24
- Panel Active Window 26
- Blank Range 26
- HSYNC Output 26
- VSYNC Output 26
- 6.9 Output Data Path 27
- 6.10 Special Output Setup 28
- Input VSYNC 29
- Output VSYNC 29
- 6.12 TCON Function 30
- 6.15 Background 2 33
- 6.17 Auto Blank Screen 34
- Input Image Window 35
- HSYNC Input 35
- VSYNC Input 35
- (Internal VD) 36
- R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 37
- G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 37
- B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 37
- 6.20.7 RGB565 38
- 6.21 Input Mode Selection 39
- Background 41
- 6.24 Scaling Engine 42
- 6.25 Timing Adjustment 45
- Pre-Image Enhancement 46
- Post-Image Enhancement 46
- 6.26.3 Sharpness Process 47
- 6.26.7 LUT Gamma Correction 48
- 6.26.8 Dither 48
- Factor 0x80 49
- 6.27 PWM Function 50
- R_PWM_REF 51
- Base on panel clock 51
- R_PWM_FREQ 51
- R_PWM_DUTY 51
- Base on reference clock 51
- 6.28.5 VBI Data Slicer 55
- 6.28.6 Source Detection 55
- 6.28.7 Luminance Process 56
- 6.28.8 Chroma Process 57
- 6.28.9 Comb Filter Process 58
- 6.28.10 AGC and ACC Process 60
- 6.28.11 AFE and PLL Control 63
- 6.30 Serial RGB Output 68
- 6.31 BIT1690 Interface 68
- 6.32 OSD Function 69
- 6.32.2 OSD Memory Mapping 70
- R_Wx_INDEXS 71
- R_Wx_INDEXE 71
- R_BANK_SEL = 000 72
- If Display RAM 72
- {0x503[4],0x403[6:0]} = 72
- {0x501[4],0x401[6:0]} 73
- R_Wx_INDEX_S 76
- R_OSD_LAYER[2:0] = 001 77
- 6.32.7 OSD Clock Control 79
- 6.33 Timer 80
- 6.34 IR Decoder Function 81
- 6.35 GPI and KEY Function 82
- 6.36 PLL and OSC Pads 82
- 6.37 Auto Detection 83
- 01: From VSYNC1 Pin 85
- 10: From HSYNC2 Pin 85
- 11: From VSYNC2 Pin 85
- 7 User Interface 86
- 7.2.1 Architecture 89
- 7.2.2 Instruction Set 91
- 7.2.3 Start and Interrupt 94
- 7.2.6 Watch Dog Timer 95
- 7.2.8 TWSI Write/Read 96
- 7.2.9 SPI Interface 96
- 7.2.10 Debug Mode 96
- 7.3 Slave Mode 97
- 7.3.2 TWSI Protocol 98
- From Pin 104 Setting 100
- From Pin 105 Setting 100
- 8 Timing Diagram 101
- 9 Electrical Characteristic 103
- 10 Soldering Information 104
- 11 Package Information 105
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