Zoom V3 1612 Manual de usuario descargar pdf (Pagina 9)

BIT1612 10-Bit Digital Video Decoder with OSD and T-CON

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Figure

Figure 4-1 BIT1612 Architecture .................................................................................................................. 3

Figure 5-1 Pin Configuration ........................................................................................................................ 4

Figure 6-1 Interrupt Function Block ............................................................................................................ 10

Figure 6-2 Double Buffer Function ..............................................................................................................11

Figure 6-3 Hardware Reset Waveform....................................................................................................... 13

Figure 6-4 Panel Timing Setup................................................................................................................... 16

Figure 6-5 Output Data Path Selection ...................................................................................................... 18

Figure 6-6 Synchronization Timing............................................................................................................. 19

Figure 6-7 Two-Fields Synchronization Timing .......................................................................................... 19

Figure 6-8 Display Layer ............................................................................................................................ 22

Figure 6-9 Free Run and Background........................................................................................................ 24

Figure 6-10 Input Window Setup................................................................................................................ 25

Figure 6-11 Input Data Path Setup............................................................................................................. 26

Figure 6-12 ITU656/656-Like (27MHz)....................................................................................................... 27

Figure 6-13 ITU601 (13.5MHz) .................................................................................................................. 27

Figure 6-14 RGB 8:8:8 (Max. 100MHz)...................................................................................................... 27

Figure 6-15 Serial-RGB (Max. 40MHz) ...................................................................................................... 27

Figure 6-16 YUV 4:4:4 (Max.100MHz) ....................................................................................................... 28

Figure 6-17 RGB 565 8:8:8 (Max. 100MHz)............................................................................................... 28

Figure 6-18 RGB 5:6:5 Setup..................................................................................................................... 28

Figure 6-19 Input Mode Selection .............................................................................................................. 30

Figure 6-20 Display Window Setup ............................................................................................................ 31

Figure 6-21 Scaling Function ..................................................................................................................... 32

Figure 6-22 Timing Adjustment VREF Information..................................................................................... 36

Figure 6-23 Image Enhancement............................................................................................................... 36

Figure 6-24 Linear Mapping ....................................................................................................................... 39

Figure 6-25 DAC Clamp ............................................................................................................................. 39

Figure 6-26 PWM Function ........................................................................................................................ 41

Figure 6-27 Video Decoder Block Diagram................................................................................................ 42

Figure 6-28 Synchronization Process ........................................................................................................ 44

Figure 6-29 Luminance Process Block....................................................................................................... 46

Figure 6-30 Chroma Process Function Block ............................................................................................ 47

Figure 6-31 AGC and Clamp Pulse............................................................................................................ 50

Figure 6-32 AGC Control Selection............................................................................................................ 50

Figure 6-33 Input Path................................................................................................................................ 54

Figure 6-34 Field Type Selection................................................................................................................ 55